This invention relates in general to digital signal transmission, and more particularly to an integrated data clock extractor for regenerating a data clock associated with a stream of data that can then be used to sample the data stream.
It is well known in traditional digital communication systems to perform clock extraction by means of an external device such as the TRU050-GACGA/20.48 clock extractor available from ATandT, LUCENT and VECTRON. This prior art circuit works very well, but is expensive and requires separate handling and assembly onto data encode/decode circuit boards.
Other well-known phase lock loop circuits are available, but they too have a negative impact on cost, board area and connectivity. They are also typically analog in nature, and do not lend themselves to easy integration into digital CMOS ASICs. Also, many traditional phase lock circuits require a regular periodic input, whereas a data stream is not a regular periodic signal.
The following prior art references disclose various types of programmable delay elements for synchronizing a clock to a data stream:
EP 0 156 375 (Honeywell)
U.S. Pat. No. 5,642,386 (Rockwell)
U.S. Pat. No. 4,805,195 (Keegan)
U.S. Pat. No. 4,338,569 (Petrich)
EP 0156375 sets forth a circuit for accurately selecting a specific pulse train from a sequence of similar, but not identical pulse trains. An up/down counter and programmable delay line are set forth. However, it would not be possible to integrate the disclosed delay line inside a digital CMOS gate array or standard cell array while still obtaining consistent delay values. This is because the actual circuit delays can vary from one half to two times the nominal values as a result of variations in process, temperature and voltage. The design of the delay line in this prior art system requires an exact amount of delay be established so that the total delay through all elements is exactly one clock cycle which, is indicated above, is not plausible to accomplish within a digital CMOS gate array or standard cell array as a result of variations in delay from process, temperature and voltage.
U.S. Pat. No. 5,642,386 sets forth a clock/data extraction technique utilizing multiple programmable delay elements arranged in series with a common control input for each element. Data bit times are framed in the input data stream within a number of fixed tap points between each delay line. Control logic is then utilize to identify the statistical midpoint of the framed bit times and which tap point is closest to the midpoint. The control logic uses a multiplexer to select the desired tap point as a stable data sample point. There is no suggestion of using a delay line for incrementally adjusting the phase of an input clock to produce an output data recovery clock whose positive edge lines up exactly with reoccurring data transitions on the bit boundaries of the data stream, as discussed in greater detail below with reference to the present invention.
U.S. Pat. No. 4,805,195 discloses a circuit to distribute clock signals in a multi-board system by means of programmable delay elements. However, there is no input data stream, nor any specific means of detecting a desired delay setting. Consequently there is no extracted data stream. Furthermore the specific delay elements set forth in this prior art document are incapable of integration into digital CMOS gate arrays because specific delays are recited which, as discussed above in connection with EP 0 156 375, renders impossible the integration of such delay elements into a CMOS gate array or standard cell array.
U.S. Pat. No. 4,338,569 discloses a configuration which ceases to operate properly if its up/down counter rolls over because a number of data bits stored in the programmable delay line would be jumped over resulting in a data error in the phase corrected output. Moreover, since the total delay in the programmable delay is required to store exactly one clock period. Such a delay is not capable of integration within a CMOS gate array or standard cell array, for the reasons discussed above in connection with EP 0 156 375.
According to the present invention, a data clock extractor is integrated into the same ASIC as the rest of the data encode/decode hardware, without the need of any external hardware. This ASIC contains bit decoding and framing hardware as well as the clock extraction hardware, thereby substantially reducing cost of the function and required PCB area when compared to prior art external clock extraction devices. Also, the circuit is designed to function in exclusively a digital environment, in contrast with prior art phase lock loop circuits. All signaling uses xe2x80x9clogic 1xe2x80x9d and xe2x80x9clogic 0xe2x80x9d type logic levels which are consistent with current digital CMOS design techniques.
The circuit according to the present invention provides a data clock extraction function by taking an arbitrary clock signal of the correct frequency, and applying a variable amount of delay to this clock signal, so to provide an extracted data clock signal with signal transitions adjusted to be coincident with the data input signal. The two primary components of the circuit according to the present invention are a programmable delay element, and a clock phase detector. In operation, the clock phase detector observes an input data stream, and the current extracted data clock, and makes small incremental changes to a delay adjust input of the programmable delay element, so that the positive transitions of the delayed data clock (i.e. the extracted data clock signal) remain almost co-incident with the positive transitions of the data stream.
In order to integrate the data clock extractor of the present invention into a digital CMOS ASIC, a cycle limit extractor limit is utilized to dynamically adjust for variations in the programmable delay element resulting from process, temperature and voltage, thereby overcoming the shortcomings of the above discussed prior art systems.